This invention relates, in general, to semiconductor devices and, more particularly, to an improved method of fabricating CMOS semiconductor devices.
The factors that have the greatest impact on the probe yield of integrated circuits are directly related to the physical size or dimensions of the chip being manufactured and to the packing density or, the number of devices that are formed within a given chip area. As the requirement for higher speeds increases, the device active area is scaled down, introducing other difficulties which had not heretofore appeared. Accordingly, the process described by M. P. Lepselter entitled "BEAM LEAD TECHNOLOGY", Bell System Journal, Vol. XLV, No. 2, February 1966 would be entirely unsatisfactory for the present high speed, high packing density art. The process described in the article is directed to fabricating beam-lead devices wherein the leads serve both a structural and electrical function and is directed to the formation of a platinum silicide ohmic contact and the subsequent formation of a lead consisting of a tri-layer of sputtered titanium, platinum, and electroformed gold.
Similary, in a recent patent to D. J. Tanguay et al. entitled "USE OF SILICIDE TO BRIDGE UNWANTED POLYCRYSTALLINE SILICONE P-N JUNCTION", which issued on June 1, 1982 as U.S. Pat. No. 4,333,099 and assigned to the same assignee as the subject application the authors chose to address the problem arising in CMOS devices where polycrystalline silicon (polysilicon) lines are utilized to interconnect various elements. However, when using polysilicon, unwanted PN junctions were allowed to be formed after which they were electrically short circuited by a section of silicide which bridged the unwanted formations. It is well known, however, that buried contact processes are able to increase packing density still further without sacrificing the performance of, for example, NMOS integrated circuits. Although the buried contact concept also appears in complementary-metal-oxide-semiconductor (CMOS) devices, the diode formed between the P+ diffusion and the N+ polysilicon or between the P+ polysilicon and N+ polysilicon has been said to have an appreciable effect on the speed of the CMOS circuit.
Accordingly, as an alternative to the prior art processes it would be highly desirable to be able to fabricate a buried contact capable of functioning with CMOS devices without the resultant requirement to short circuit or otherwise remove the buried contact diode. It is also imperative for the success of any such device that the fabrication complexity not be increased and that the speed of the device is increased.